In digital electronic systems, bi-directional off-chip driver/receiver circuits, or I/O buffers, are used to transfer digital signals between integrated circuit chips connected to a common bus. The I/O buffers give each chip a capability to present digital information to the bus in drive mode, as well as to "listen" for data on the bus in the receive mode. When data is to be driven onto the bus, the integrated circuit or chip internal drive logic will present the data input signal DI to an input node of an I/O buffer. The driver is controlled by an inhibit signal INH, and when the inhibit signal INH is disabled, the data input signal DI will be propagated to the I/O data output node providing a data output signal DOUT, for driving off-chip. The DOUT node is connected to a chip I/O pad. When the inhibit node is enabled, the driver output is put into a high impedance state allowing the input buffer to receive signals from the bus at the DOUT pin. The receiver output is presented to the chip-internal receive logic at the DATA IN node.
To reduce component and system test complexity and cost, many system designs require each component to support boundary scan testing. Boundary scan techniques provide test access to chip-internal nodes, permit interconnect tests between components, and allow I/O buffers to be tested without having to contact the buffer pads. To accommodate boundary scan testing, a two-to-one multiplexor is added to the basic I/O buffer cell. The multiplexor provides a path for test data as well as functional data to be presented to the chip-internal receive logic. The paths through the multiplexor function are selected by an SEL node. To test the I/O buffer, the SEL pin is disabled allowing the test data present at the multiplexor node to be gated to the chip-internal receive logic at the DATA IN node. In operational mode, the SEL node is enabled thereby allowing data from the receiver input buffer to propagate to the DATA IN node.
In high performance digital systems, data processing associated with the chip-internal receive logic require that the data on the bus be sampled even when the chip is driving the bus. When the I/O buffer is driving, data presented to the DI node is propagated to the DOUT node as well as to the input of the receiver. The data propagates through the receiver and multiplexor, and is presented to the chip-internal receive logic at the DATA IN node. This mode of operation, however, creates several problems. The input receiver buffer is coupled to the same node as the chip I/O pad. The I/O pad is part of a transmission line involving other chips and their associated I/O pads and I/O buffer interconnections. When data is launched from the I/O buffer, signal reflections are produced on the bus due to impedance mismatches along the net. If the data is sampled at the source before the reflections are cancelled, erroneous signals could be captured creating data integrity problems for the chip-internal receive logic. To avoid that situation, the conventional approach is to bypass the input receive buffer using a multiplexor external to the I/O buffer cell. The inhibit pin will select the bypass path through the external multiplexor when the I/O buffer is in drive mode, providing a stable value of the driven data directly to the chip-internal receive logic.
There are, however, several drawbacks using the external multiplexor to accomplish the receiver bypass function. Each I/O buffer cell requires a two-to-one multiplexor circuit. For high I/O count chips, this can potentially use a significant amount of silicon area on the chip. Each multiplexor requires one connection to the I/O buffer cell and three connections to the chip-internal receive logic. These interconnects contribute to global wiring congestion within the chip. This, in turn, tends to make the task of wiring the chip more difficult and can even force other global wire interconnections to become longer due to increased congestion. The multiplexor interconnect wire RC delay as well as the propagation delay through the multiplexor circuit itself, add to the overall delay of the bypass path. The external multiplexor creates an additional load capacitance on the chip-internal drive logic that generates the D1 signal thereby adding further delay to the path. The chip-internal receive logic processing that uses the driven data, tend to be timing-critical. Therefore it is imperative that the receiver bypass delay be as small as possible so as not to lengthen the chip clock cycle time which would degrade system performance. Accordingly, there is a need for an enhanced method and apparatus which is effective to implement the above described receiver bypass function, while at the same time reducing the signal propagation delay and wire congestion penalties typically incurred in connection with conventional and previous receiver bypass designs, as well as minimizing chip silicon area requirements.